1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to the structure of a fuse area and a method for forming the fuse area.
2. Description of the Related Art
Generally, semiconductor devices are formed by stacking material layers of various patterns and finally depositing a protection film called a passivation film. The passivation film, conventionally formed of a hard film such as a silicon nitride film, protects semiconductor devices, especially by absorbing mechanical, electrical and chemical shocks during a subsequent assembly or packaging process.
Normally, a repair process is performed on semiconductor devices such as memory devices when their circuits do not properly operate due to defects that occur during manufacturing. The defective circuits may be replaced with redundant circuits, or a trimming process may be performed in which the characteristics of some circuits are modified for a given application. The repair or trimming process is performed by methods such as cutting (severing) certain wirings using irradiation of a laser beam. The wirings, portions of which are to be severed by the irradiation of a laser beam, are referred to as fuse lines, and an area including the severed portions (wiring) and a region surrounding the severed portions is referred to as a fuse area.
FIG. 1 is a sectional view of a conventional semiconductor device, particularly, a sectional view for showing a portion of a memory cell and a fuse area in a dynamic random access memory (DRAM) device employing a multi-level interconnect wiring structure. A cell array area is shown on the left side of FIG. 1. The cell array area includes a memory cell composed of a transistor (14, 16 and 18) and a capacitor (30, 32 and 34), multi-level interconnect wirings 38 and 42, interlayer insulating films 20, 26, 36 and 40 and a passivation film 44. A fuse area is shown on the right side of FIG. 1. The fuse area includes a fuse line, that is, a bit line 24 connected to the drain region 16 of the transistor via a bit line contact. The fuse area further includes a fuse opening portion A formed by etching a predetermined depth and width of the interlayer insulating films 36 and 40 and the passivation film 44 on the fuse line 24. The fuse opening portion A is irradiated with a laser beam, thereby cutting the underlying fuse line 24 (This laser cutting step not shown in FIG. 1).
For simplicity, each of the interlayer insulating films 20, 26, 36 and 40 is illustrated as a single film but can be formed of a multi-layer film. In addition, a lower-electrode contact 28 is provided for electrically connecting the source region 18 of the transistor with the lower electrode 30 of the capacitor. The capacitor is placed on a plane different from that of the bit line 24 and thus does not contact the bit line 24. Here, the bit line 24 is described as a fuse line, but the fuse line is not limited to the bit line and may be a word line 14 or another wiring. These features are also included in the embodiments of the present invention to be described herein.
The fuse area of a conventional semiconductor device having a structure as shown in FIG. 1 has various problems. Particularly, each of the interlayer insulating films 26, 36 and 40, which are exposed by the fuse opening portion A, is usually formed of an insulating material of the silicon oxide family. For example, a borophosphosilicate glass (BPSG) film, a phosphorous silicate glass (PSG) film, a spin on glass (SOG) film, a tetra ethyl orthosilicate (TEOS) film and an undoped silicate glass (USG) film which exhibits excellent step coverage are used for the interlayer insulating films 26, 36 and 40 to alleviate a large step-difference problem in the cell array area. However, films containing a large amount of impurity, such as the above described BPSG film, PSG film, SOG film and TEOS film, in which boron (B) exceeds 5 weight percent and phosphorous (P) exceeds 4 weight percent, cannot withstand much moisture. Moisture may permeate the device through such films. As a result, metal interconnects, for example, the interconnect wirings 38 and 42 formed of aluminum, corrode, thereby degrading the reliability of semiconductor devices.
Referring now to FIG. 2, to solve this problem, Japanese Patent Publication No. Hei 9-69571 suggests forming a guard ring 38xe2x80x2 and 42xe2x80x2 in a quadrilateral shape surrounding a fuse opening portion A as shown in FIG. 2. The guard ring 38xe2x80x2 and 42xe2x80x2 is a two-layer structure, which may be formed of the same material as multi-level interconnect wirings 38 and 42, e.g., aluminum, and may be simultaneously formed with the multi-level interconnect wirings 38 and 42, respectively. In addition, an etch stop layer 34xe2x80x2 having a quadrilateral border shape is formed under the guard ring 38xe2x80x2 to stop etching of an interlayer insulating film 36 during etching for forming a guard ring opening portion. The etch stop layer 34xe2x80x2 may be formed of the same material as an upper electrode 34 of a capacitor, e.g., polysilicon, and may be simultaneously formed with the upper electrode 34.
Accordingly, the guard rings 38xe2x80x2 and 42xe2x80x2 block moisture permeating through the interlayer insulating films 36 and 40, which comprise the side wall of the fuse opening portion A, thereby improving the device reliability. However, moisture may permeate the device through an interlayer insulating layer 26 where a guard ring is not formed. Particularly, because the guard rings 38xe2x80x2 and 42xe2x80x2 are formed as a multi-layer structure, moisture may permeate through the interfaces among the interlayer insulating films 26, 36 and 40 which are vulnerable to moisture coming through the interface between the layers of the guard rings 38xe2x80x2 and 42xe2x80x2. Moreover, a layout area increases due to the additional formation of guard rings 38xe2x80x2 and 42xe2x80x2, thereby decreasing the high integration density of semiconductor devices.
To solve the above problems, it is a first object of the present invention to provide a semiconductor device having a fuse area better protected at preventing moisture-permeation and allowing for efficient cutting of fuses.
It is a second object of the present invention to provide a method for forming a fuse area of a semiconductor device, which is better at preventing moisture-absorption and allows for efficient cutting of fuses.
Accordingly, to achieve the first object, the present invention provides a semiconductor device having a multi-level interconnect wiring structure and a fuse opening portion which allows cutting of a fuse line. The semiconductor device includes a guard ring having a quadrilateral border shape surrounding the fuse opening portion, for blocking permeation of moisture through the fuse opening portion; an etch stop layer formed over the fuse line and at least under the guard ring; a multi-layer interlayer insulating layer structure formed on the entire surface of a substrate including the etch stop layer, the multi-layer interlayer insulating layer structure containing the guard ring, wherein the fuse opening portion is formed in the multi-layer interlayer insulating layer structure; and a passivation layer formed on the entire surface of the substrate including the guard ring and the multi-layer interlayer insulating layer structure and is etched to expose the fuse opening portion. The guard ring vertically extends from the etch stop layer to the uppermost wiring of the multi-layer interconnect wirings.
The guard ring is formed of a material for forming the uppermost wiring of the multi-level interconnect wirings or the passivation layer.
The semiconductor device also includes a moisture barrier layer over or under the etch stop layer.
To achieve the second object, the present invention provides a method for forming a fuse area of a semiconductor device. Primarily, an etch stop layer is formed over the fuse line and at least in a region in which the guard ring is formed. A multi-layer interlayer insulating layer structure is formed on a substrate including the etch stop layer. The multi-layer interlayer insulating layer structure is etched until part of the etch stop layer is exposed so as to form a guard ring opening portion. The guard ring is formed by filling the guard ring opening portion with a predetermined material. The guard ring opening portion vertically extends from the etch stop layer to the uppermost wiring of the multi-level interconnect wirings.
The guard ring is formed of a material for forming an uppermost wiring or the material of a passivation layer and formed simultaneously with the uppermost wiring or the passivation layer.
The method also includes the step of forming a moisture barrier layer at least under the regions in which the guard ring and the fuse opening portion are formed, before or after the step of forming the etch stop layer.
The etch stop layer may be separately formed in a region in which the guard ring opening portion is formed and in a region in which the fuse opening portion is formed so that the etch stop layer can be used as an etch stop layer when forming the guard ring opening portion and when forming the fuse opening portion.
According to the present invention, the guard ring is formed at one time using the passivation layer or the uppermost wiring, thereby efficiently preventing permeation of moisture through the interface between the interlayer insulating films.
In addition, when the guard ring is simultaneously formed with the uppermost interconnect wiring, the passivation layer is etched to expose the part of the guard ring when forming the fuse opening portion, thereby minimizing an increase in a layout area due to formation of the guard ring.
Moreover, according to an embodiment of the present invention, the etch stop layer is used when an etching process is performed for forming the fuse opening portion so that the thickness of an interlayer insulating film remaining on the fuse line can be accurately controlled as compared with a conventional method of forming a fuse opening portion using timed etching, thereby improving the cutting efficiency of a fuse.